1. Field of the Invention
The invention relates to a phase locked loop (PLL) and, in particular, to a PLL with a charge pump-based frequency modulator.
2. Description of the Related Art
The most popular architecture used for frequency/phase modulation is a closed loop modulator with a digital pre-emphasis filter. Although most of the phase locked loop (PLL) circuits work in the digital domain, the PLL transfer function, which consists of analog components, is still required, to design a pre-emphasis filter for obtaining high modulation bandwidth. The mismatch between the pre-emphasis filter and the PLL closed-loop transfer function induces phase errors. To minimize phase errors, accurate PLL dynamics need to be captured and associated loop parameters must be calibrated and controlled with additional adaptive circuitry. Several circuit topologies have been disclosed by various researchers to alleviate this mismatch problem such as using switching capacitor circuits with active devices and a type I loop filter, automatic calibration architecture, and a frequency discriminator. Although mismatch can be minimized through such design efforts, loop filter calibration is still required to minimize phase error, thus, increasing complexity of circuit implementation. Additionally, boosting the modulation signal from the sigma-delta modulator (SDM), introduces large amounts of jitter to the PLL input. For such an example, a larger dynamic range of the charge pump circuit is required. Thus, resulting in increased noise levels due to greater clock feed-through induced by larger variations.
Another architecture for a DFM is two-point-modulation, in which high data rates are achieved by modulating the SDM and the voltage-controlled oscillator (VCO) at the same time. To achieve high fidelity modulation, a VCO gain with a large linearity range is required. However, this would increase the VCO design complexity due to the tradeoffs between linearity and gain. For two-point-modulation, accurate VCO gain calibration is unavoidable and, the phase error actually induced by the VCO gain variation is more sensitive than that of the digital pre-emphasis architecture, thus, implying that higher precision tuning is needed. No obvious solution without tuning was disclosed in the literature.
The invention discloses and verifies in silicon a hybrid time/digital fractional-N PLL in which phase errors are corrected linearly using a passive pseudo-differential circuit topology without an operational amplifier. An accurate VCO gain, which had 1 KHz resolution, was obtained by digitally calibrating the closed loop gain. Exploiting the simplicity and the calibration precision of the PLL, a programmable charge pump was incorporated in the original architecture to build a new DFM that can achieve modulation at high data rates without any of the previously mentioned drawbacks. Specifically, phases can be easily modulated using a programmable charge pump that is essentially of high bandwidth and resolution. Not only is the circuit complexity greatly reduced, but also the charge pump circuitry, as digital circuits, were shown as scaling very well. By modulating the PLL from both the SDM and the programmable charge pump, a data rate up to the PLL's theoretical limit was achieved. The strength of the disclosed architecture was supported by both analytical analysis and simulation results.